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ISL6423B
Data Sheet April 10, 2007 FN6412.1
Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
The ISL6423B is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of singe antenna ports. The device consists of a current-mode boost PWM and a low-noise linear regulator along with the circuitry required for 22kHz tone generation, modulation and I2C device interface. The device makes the total LNB supply design simple, efficient and compact with low external component count. The current-mode boost converters provides the linear regulator with input voltage that is set to the final output voltages, plus typically 0.8V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drop across the linear pass element while permitting adequate voltage range for tone injection. The final regulated output voltage is available at output terminals to support the operation of an antenna port for single tuners. The outputs for each PWM can be controlled in two ways, full control from I2C using the VTOP and VBOT bits or set the I2C to the lower range i.e., 13V/14V, and switch to higher range i.e., 18V/19V, with the SELVTOP pin. All the functions on this IC are controlled via the I2C bus by writing 8 bits words onto the System Registers (SR). The same register can be read back, and five I2C bits will report the diagnostic status. Separate enable command sent on the I2C bus provides for standby mode control for the PWM and linear combination, disabling the output and forcing a shutdown mode. The output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed to four levels. The External modulation input EXTM can accept a modulated Diseqc command and transfer it symmetrically to the output. Alternatively the EXTM pin can be used to modulate the continuos internal tone. The FLT pin serves as an interrupt for the processor when any condition turns OFF the LNB controller (Over Temperature, Overcurrent, Disabled). The nature of the Disable can be read of the I2C registers.
Features
* Single Chip Power solution - Operation for 1-Tuner/1-Dish Applications - Integrated DC/DC Converter and I2C Interface * Switch-Mode Power Converter for Lowest Dissipation - Boost PWMs with >92% Efficiency - Selectable 13.3V or 18.3V Outputs - Digital Cable Length Compensation (1V) - I2C and Pin Controllable Output * Output Back Bias Capability of 28V * I2C Compatible Interface for Remote Device Control * Registered Slave Address 0001 00XX * 2.5V, 3.3V, 5V Logic Compatible * External Pin to Toggle Between V and H Polarization * Built-In Tone Oscillator Factory Trimmed to 22kHz - Facilitates DiSEqC (EUTELSAT) Encoding - External Modulation Input * Internal Over-Temperature Protection and Diagnostics * Internal OV, UV, Overload and Overtemp Flags (Visible on I2C) * FLT signal * LNB Short-Circuit Protection and Diagnostics * QFN, EPTSSOP Packages * Pb-Free Available (RoHS Compliant)
Applications
* LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART NUMBER* ISL6423BERZ (Note) PART MARKING 6423BERZ TEMP. (C) PACKAGE PKG. DWG. # L24.4x4D
-20 to +85 24 Ld 4x4 QFN (Pb-free)
ISL6423BEVEZ ISL6423BEVEZ -20 to +85 28 Ld EPTSSOP M28.173B (Pb-free) (Note) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Add "-T" suffix for tape and reel.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Pinouts
ISL6423B (28 LD EPTSSOP) TOP VIEW
VCC 1 NC 2 FLT 3 SGND 4 SGND 5 TCAP 6 ADDR0 7 ADDR1 8 BYPASS 9 PGND 10 GATE 11 VSW 12 NC 13 CS 14 28 CPSWIN 27 CPSWOUT 26 CPVOUT 25 EXTM 24 SDA 23 SCL 22 TDOUT 21 TDIN 20 VO 19 NC 18 NC 17 AGND 16 SELVTOP 15 TXT
ISL6423B (24 LD QFN) TOP VIEW
CPSWOUT 20 CPVOUT 19 18 17 16 15 14 13 7 GATE 8 VSW 9 CS 10 TXT 11 SELVTOP 12 AGND EXTM SDA SCL TDOUT TDIN VO CPSWIN 21
SGND
24 SGND TCAP ADDR0 ADDR1 BYPASS PGND 1 2 3 4 5 6
23
22
2
VCC
FLT
FN6412.1 April 10, 2007
Block Diagram
11 OLF/BCF DCL OC1 CLK1 SDA SCL 6 PGND ISELL&H EN ENT ILIM1 CS AMP 9 CS + VTOP VBOT CLK1 OSC. OLF/BCF OUVF ADDR0 ADDR1 OTF THERMAL SHUTDOWN SELVTOP COUNTER OVERCURRENT PROTECTION LOGIC SCHEME 1 PWM LOGIC 7 GATE Q S ADDR0 ADDR1 SDA SCL FLT CHARGE PUMP CPVOUT OUVF TTH DCL 19 17 16 3 4 23
TONE DECODER 14 TDIN
TXT TTH
8
VSW MSEL1
13 12
VO AGND + -
22 1 24
VCC SGND SGND
ON CHIP LINEAR UVLO POR SOFT-START BYPASS EXTM ENT1
EN1/EN2
NOTE:
5
10
2
18
20
CPSWIN
21
1. Pinouts shown are for the QFN package.
TCAP
TXT
INT 5V SOFT-START
CPSWOUT
-
+
3
15 TDOUT
FN6412.1 April 10, 2007
I2 C INTERFACE
SLOPE COMPENSATION
BAND GAP REF VOLTAGE BGV REF VOLTAGE ADJ1 TONE INJ CKT
DIV & WAVE SHAPING
VREF1
INT TONE
EXT TONE CKT
Typical Application Schematic QFN
VIN
RTN 0 FLT BAR EXTM
24 23 22 21 20 19
SGND FLT VCC CPSWIN CPSWOUT CPVOUT
0 0 1 2 3
GATE VSW CS TXT SELVTOP AGND
7 8 9 10 11 12
1
6 5 4
4
C24 1F 0 C27 0.22F C23 56F 0 R10 18 C26 1F 1 2 3 4 5 6 2 L5 15H R8 0.1 TPC6002 Q2 R9 470 C21 100pF 0 D5 1 CMS06 C22 56F 0 C18 10F 0 L6 4.7H 2 C19 10F 0 C20 10F 0 0
FN6412.1 April 10, 2007
C29 1n
R11 C25 47n 0 R12
100 100 L4 220H 1 C15 2 0.22F 15
SDA SCL
D6 CMS06 18 17 16 15 14 13 C28 0.1F R23 10k
R7
VLNB
SGND EXTM TCAP SDA ADDR0 U2 SCL ADDR1 ISL6423ER TDOUT BYPASS TDIN PGND VO
M6 NDS356AP R24 4.7k R13 4.7k D8 1.5KE24
C16 10n
Q4 2N2222A
RTN
R22 47k
TXT TDOUT SELVTOP D7 CMS06
NOTE : SDA and SCL require pull up to the required logic level.
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V Logic Input Voltage Range (SDA, SCL, ENT, DSQIN 1 and 2, SEL18V 1 and 2) . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 2, 3) JA (C/W) JC (C/W) QFN Package (Notes 2, 3) . . . . . . . . . . 38 4.5 EPTSSOP Package (Notes 2, 3) . . . . . 35 2.5 Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . -40C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . . -20C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 4. +150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150C junction may trigger the shutdown of the device even before +150C, since this number is specified as typical.
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = +25C. EN = H, VTOP VBOT = L, ENT = L, DCL = L, IOUT = 12mA, unless otherwise noted. See software description section for I2C access to the system. SYMBOL TEST CONDITIONS MIN 8 EN = L IIN EN = VTOP = VBOT = ENT = H, No Load TYP 12 1.5 4.0 MAX 14 3.0 8.0 UNITS V mA mA
PARAMETER Operating Supply Voltage Range Standby Supply Current Supply Current UNDERVOLTAGE LOCKOUT Start Threshold Stop Threshold Start to Stop Hysteresis SOFT-START COMP Rise Time (Note 5) Output Voltage (Note 5)
7.5 7.0 350
400
7.95 7.55 500
V V mV
(Note 5) VO1 VO1 VO1 VO1 (Refer to Table 1) (Refer to Table 1) (Refer to Table 1) (Refer to Table 1) VIN = 8V to 14V; VO = 13.3V VIN = 8V to 14V; VO = 18.3V IO = 0mA to 350mA IO = 0mA to 750mA DCL = 0, ISEL H = 0, ISEL L = 0 (Note 8) DCL = 0, ISEL H = 0, ISEL L = 1 (Note 8) DCL = 0, ISEL H = 1, ISEL L = 0 (Note 8) DCL = 0, ISEL H = 1, ISEL L = 1 (Note 8)
13.04 14.02 17.94 19.00 275 515 635 800 -
8196 13.3 14.3 18.3 19.3 4.0 4.0 50 100 305 570 705 890 900 51 1000 10
13.56 14.58 18.66 19.68 40.0 60.0 80 200 345 630 775 980 20
Cycles V V V V mV mV mV mV mA mA mA mA ms ms mA mA
Line Regulation
DVO1, DVO2 DVO1, DVO2 IMAX
Load Regulation
Dynamic Output Current Limiting
Dynamic Overload Protection Off Time Dynamic Overload Protection On Time Static Output Current Limiting Cable Fault CABF Threshold
TOFF TON IMAX ICAB
DCL = 0, Output Shorted (Note 8)
DCL = 1 (Note 8) EN = 1, VO = 19V, No Tone.
2
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FN6412.1 April 10, 2007
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = +25C. EN = H, VTOP VBOT = L, ENT = L, DCL = L, IOUT = 12mA, unless otherwise noted. See software description section for I2C access to the system. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER TONE OSCILLATOR Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time TONE DECODER Input Amplitude Frequency Capture Range Input Impedance Detector Output Voltage Detector Output Leakage Tone Decoder Rx Threshold Tone Decoder Tx Threshold LINEAR REGULATOR Drop-out Voltage Output Backward Leakage Current Output Backward Leakage Current Output Backward Current Threshold Output Backward Current Limit Output Backward Voltage Output Under Voltage (Asserted high during soft-start) Output Over Voltage (Asserted high during soft-start)
ftone Vtone dctone Tr, Tf
ENT = H ENT = H, IO = 5mA ENT = H, ENT = H,
20.0 500 40 5
22.0 680 50 10
24.0 800 60 14
kHz mV % s
Vtdin Ftdin Zdet Vtdout_L Itdout_H VRXth VTXth Tone Present, ILOAD = 3mA Tone absent, VO = 6V TXT = L and TTH = 0 (Note 9) TXT = H and TTH = 0 (Note 9)
200 17.5 100 400
8.6 150 450
1000 26.5 0.4 10 200 500
mV kHz k V A mV mV
IOUT = 750mA IBKLK IBKLK IBKTH IBKLM VOBK EN = 0; VOBK = 27V EN = 0; VOBK = 28V EN = 1; VOFAULT = 19V (Note 7) EN = 1; VOFAULT = 19V (Note 7) EN = 0 OUVF bit is asserted high, Measured from the typ. output set value OUVF bit is asserted high, Measured from the typ. output set value
-6 +2
0.8 2.0 3.0 140 350 -
1.05 3.0 17 27 -2 +6
V mA mA mA mA V % %
TXT, EXTM, SELVTOP AND ADDR 0/1 INPUT PINs (Note 8) Asserted LOW Asserted HIGH Input Current CURRENT SENSE (CS pin) Input Bias Current Overcurrent Threshold ERROR AMPLIFIER Open Loop Voltage Gain Gain Bandwidth Product PWM Maximum Duty Cycle Minimum Pulse Width 90 93 20 % ns AOL
GBP
1.7 -
25
0.8 -
V V A
IBIAS VCS Static current mode, DCL = H
325
700 450
500
nA mV
-
93 14
-
dB MHz
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FN6412.1 April 10, 2007
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = +25C. EN = H, VTOP VBOT = L, ENT = L, DCL = L, IOUT = 12mA, unless otherwise noted. See software description section for I2C access to the system. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER OSCILLATOR Oscillator Frequency Thermal Shutdown Temperature Shutdown Threshold Temperature Shutdown Hysteresis OTFI FLT (released) FLT (asserted) NOTES: 5. Internal digital soft-start
fo
Fixed at (20)(ftone)
396
440
484
kHz
-
150 20
-
C C
VO = 6V ISINK = 3.2mA
-
-
10 0.4
A V
6. EXTM, TXT and SELVTOP and addr 0/1 pins have 200k internal pulldown resistors. 7. On exceeding this backward current limit threshold for a period of 2ms, the device enters the Backward dynamic current limit mode (350mA typ) and the BCF I2C bit is set. The dynamic current limit duty ratio during a back current fault is ON = 2ms/OFF = 50ms. The output will remain clamped to the fault output voltage till released. On removal of the fault condition the device returns to normal operation 8. In the Dynamic current limit mode the output is ON for 51ms and OFF for 900ms. But remains continuously ON in the Static mode. When tone is ON the minimum current limit is 50mA lower the values indicated in the table.
Tone Waveform
ENT I2C
MSEL I2C
EXTM PIN
VOUT PIN 22kHz 22kHz 22kHz 22kHz 22kHz 22kHz INTERNAL TONE INTERNAL TONE Tr = 10s TYP EXTERNAL TONE Tr = 10s TYP RETURNS TO NOMINAL VOUT ~1 PERIOD AFTER THE LAST EXTM RISING EDGE T > 55s;
NOTES: 9. The signal pin TXT changes the decoder threshold during tone transmit and receive. TTH allows threshold control through I2C. 10. The tone rise and fall times are not shown due to resolution of graphics. It is 10s typ for 22kHz. 11. The EXTM pins have input thresholds of Vil(max) = 0.8V and Vih(min) = 1.7V FIGURE 1. TONE WAVEFORM
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FN6412.1 April 10, 2007
Typical Performance Curves
0.80 0.70 0.60 IOUT (A) 0.50 0.40 0.30 0.20 0.10 0.00 0 20 40 TEMPERATURE (C) 60 80 IOUT_max IOUT (A) 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0 20 40 TEMPERATURE (C) 60 80 IOUT_max
FIGURE 2. OUTPUT CURRENT DERATING (EPTSSOP)
FIGURE 3. OUTPUT CURRENT DERATING (4x4 QFN)
Functional Pin Description
SYMBOL SDA SCL VSW PGND CS SGND TCAP BYPASS TXT VCC GATE VO ADDR0 & ADDR1 EXTM Bidirectional data from/to I2C bus. Clock from I2C bus. Input of the linear post-regulator. Dedicated ground for the output gate driver of respective PWM. Current sense input; connect the sense resistor Rsc at this pin for desired peak overcurrent value for the boost FET. The set peak limit is effective in the static mode current limit only i.e., DCL = HIGH. Small signal ground for the IC. Capacitor for setting rise and fall time of the output voltage. Typical value is 0.1F. Bypass capacitor for internal 5V. TXT is the Tone Transmit signal input used to change the Tone Decoder Threshold from TXT = 0, 200mV max during Receive to TXT = 1, 400mV min during Transmit. Main power supply to the chip. This output drives the boost FET gate. The output is held low when VCC is below the UVLO threshold. Output voltage for the LNB is available at VO pin. Logic combination at the ADDR0 & 1 can select four different chip select addresses. This pin can be used in two ways: 1) As an input for externally modulated Diseqc tone signal which is transferred to the symmetrically onto VOUT 2) Alternatively apply a Diseqc modulation envelope which modulates an internal tone and then transfers it symmetrically onto VOUT This is an Open Drain output from the controller. When the FLT goes low it indicates that an Over Temperature, Over load fault, UVLO, or an I2C reset condition has occurred. The processor should then look at the I2C register to get the actual cause of the error. A high on the FLT indicates that the device is functioning normally. A 47n charge pump decoupling capacitor is to be connected to CPVOUT. Connect a 1.5n capacitor between CPSWIN and CPSWOUT When this pin is low the VOUT is in the 13V, 14V range selected by the I2C bit VBOT. When this pin is high the 18V, 19V range selected by the I2C bit VTOP. The Voltage select pin enable VSPEN I2C bit must be set low for the SELVTOP pins to be active. Setting VSPEN high disables this pins and voltage selection will be done using the I2C bits VBOT and VTOP only. TDIN is the tone decoder input and TDOUT is the tone detector output. TDOUT is an open drain output FUNCTION
FLT
CPVOUT, CPSWIN CPSWOUT SELVTOP
TDIN, TDOUT
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FN6412.1 April 10, 2007
Functional Description
The ISL6423B single output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. The device utilizes built-in DC/DC step up converters that, operates from a single supply source ranging from 8V to 14V, and generates the voltage needed to enable the linear post-regulator to work with a minimum of dissipated power. An undervoltage lockout circuit disables the device when VCC drops below a fixed threshold (7.5V typ).
Linear Regulator
The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.75F. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN = LOW), the PWM power block is disabled. When the regulator blocks are active (EN = HIGH and VSPEN = LOW), the output can be controlled via I2C logic to be 13V/14V or 18V/19V (typical) by means of the VTOP and VBOT bits (Voltage Select) for remote controlling of non-DiSEqC LNBs. When the regulator blocks are active (EN = HIGH and VSPEN = HIGH), the VBOT and SELVTOP pin will control the output between 13V and 14V and the VTOP and SELVTOP pin will control the output between 18V and 19V.
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSEqC (EUTELSAT) standards. No further adjustment is required. The tone oscillator can be controlled either by the I2C interface (ENT bit) or by a dedicated pin (EXTM) that allows immediate DiSEqC data encoding separately for each LNB. All the functions of this IC are controlled via the I2C bus by writing to the system registers. The same registers can be read back, and four bits will report the diagnostic status. The internal oscillator operates the converters at twenty times the 22k tone frequency. The device offers full I2C compatibility, and supports 2.5V, 3.3V or 5V logic, up to an operational speed of 400kHz. If the Tone Enable (ENT) bit is set LOW and the MSEL bits set LOW through I2C, then the EXTM terminal activates the internal tone signal, modulating the DC output with a 680mVPP typical symmetrical tone waveform. The presence of this signal usually provides the LNB with information about the band to be received. Burst coding of the tone can be accomplished due to the fast response of the EXTM input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols. When the ENT bit is set HIGH, a continuous 22kHz tone is generated regardless of the EXTM pin logic status for the regulator channel LNB-A. The ENT bit must be set LOW when the EXTM pin is used for DiSEqC encoding. The EXTM accepts an externally modulated tone command when the MSEL I2C bit is set HIGH and ENT is set LOW.
Output Timing
The output voltage rise and fall times can be set by an the external capacitor on the TCAP pin. The output rise and fall times is given by the equation:
327.6T C = -----------------V (EQ. 1)
Where C is the TCAP value in nF, T is the required transition time in ms and V is the differential transition voltage from low output voltage range to the high output range in Volts. The maximum recommended value for TCAP is 0.15F. Too large a value of TCAP prevents the output from rising to the nominal value, within the soft-start time when the error amplifier is released. Too small a value of the TCAP can cause high peak currents in the boost circuit. For example, a 10V/ms slew on a 80F VSW capacitor with an inductor of 15H can cause a peak inductor current of approximately 2.3A.
Current Limiting
Dynamic current limiting block has four thresholds that can be selected by the ISEL H and ISEL L bits of the SR. Refer to Table 8 and Table 9 for threshold selection using these bits. The DCL bit has to be set to low for this mode of operation. In the dynamic overcurrent mode a fault exceeding the selected overcurrent threshold for a period greater than 51ms, will shutdown the output for 900ms, during which the I2C bit OLF is set high. At the end of 900ms the OLF bit is returned to the low state, a soft-start cycle (~20ms long) is initiated to ramp VSW and VOUT back up. If the fault is still present the overcurrent will be reached early in the soft-start cycle and the 51ms shutdown timer will be started again. If the fault is still present at the end of the 51ms, the OLF bit is again set high and the device once again enters the 900ms OFF time. This dynamic operation greatly reduces the power dissipation in a short circuit condition, while still ensuring excellent power-on start-up in most conditions.
DiSEqC Decoder
TDIN is the input to the tone decoder. It accepts and the tone signal derived from the VOUT thru the 10nF decoupling capacitor. The detector threshold can be set to 200mV max in the Receive mode and to 400mV min in the Transmit mode by means of the logic presented to the TXT pin. If tone is detected the open drain pin TDOUT is asserted low. This enables the tone diagnostics to be performed, apart from the normal tone detection function.
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FN6412.1 April 10, 2007
However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is selected. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a predetermined interval. When in static mode, the OLF bit goes HIGH when the current clamp limit is reached and returns LOW at the end of initial power-on soft-start. In the Static mode the output current through the linears is limited to a 990mA typ. When a 19.3V line is connected onto a VOUT1 or 2 that has been set to 13.3V the linear will then enter a back current limited state. When a back current of greater than 140mA typical is sensed at the lower FET of the linear for a period greater that 2ms the output is disabled for a period of 50ms and the BCF bit is set. If the 19.3V remains connected, the output will cycle through the ON = 2ms/OFF = 50ms. The output will return to the setpoint when the fault is removed. BCF bit is set high during the 50ms OFF period.
I2C Bus Interface for ISL6423B
(Refer to Philips I2C Specification, Rev. 2.1) Data transmission from main microprocessor to the ISL6423B and vice versa takes place through the two wire I2C bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stages of ISL6423B will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100Kbps in the standard-mode or up to 400Kbps in the fast-mode. The level of logic "0" and logic "1" is dependent of associated value of VDD as per electrical specification table. One clock pulse is generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 4.
Thermal Protection
This IC is protected against overheating. When the junction temperature exceeds +150C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. When the junction is cooled down to +130C (typical), normal operation is resumed and the OTF bit is reset LOW. If a part is repeatedly driven to the overtemp shutdown temperature the chip is latched off after the fourth occurrence and the I2C OTF bit is latched high and FLT_bar low. This OTF counter and FLT_bar can be reset and the chip restarted by either a power down/up and reload the I2C or power can be left on and the reset accomplished by toggling the I2C bit EN low then back high.
SDA
SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED
FIGURE 4. DATA VALIDITY
External Output Voltage Selection
When the I2C bit VSPEN is set high the output voltage can be selected by the I2C bus. Additionally, the package offers the pin SELVTOP for independent 13 thru 19V output voltage selection., when the VSPEN bit is set low. A summary of the voltage control is given in Table 1. For further details refer to the individual registers SR1 and SR3
TABLE 1. VSPEN 0 0 0 0 1 1 1 1 VTOP x x 0 1 0 0 1 1 VBOT 0 1 x x 0 1 0 1 SELVTOP 0 0 1 1 x x x x VOUT 13.3V 14.3V 18.3V 19.3V 13.3V 14.3V 18.3V 19.3V
START and STOP Conditions
As shown in Figure 5, START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
SDA
SCL S START CONDITION P STOP CONDITION
FIGURE 5. START AND STOP WAVEFORMS
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FN6412.1 April 10, 2007
Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).
ISL6423B Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown below in Table 2: * A start condition (S) * A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I2C slave address for the ISL6423B is 0001 0XXX) * A sequence of data (1 byte + Acknowledge) * A stop condition (P)
TABLE 2. INTERFACE PROTOCOL S0 0 0 1 0 A1 A0 R/W ACK Data (8 bits) ACK P
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 6). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.) The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6423B will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.
SCL 1 SDA 2 8 9
System Register Format
* R, W = Read and Write bit * R = Read-only bit All bits reset to 0 at Power-On TABLE 3. STATUS REGISTER (SR1) R, W SR1H R, W SR1M R, W SR1L R OTF R CABF R OUVF R OLF R BCF
TABLE 4. TONE REGISTER (SR2)
MSB START ACKNOWLEDGE FROM SLAVE
R, W SR2H
R, W SR2M
R, W SR2L
R, W ENT
R, W MSEL
R, W TTH
R, W X
R, W X
FIGURE 6. ACKNOWLEDGE ON THE I2C BUS
TABLE 5. COMMAND REGISTER (SR3) R, W R, W R, W R, W DCL R, W VSPEN R, W X R, W R, W
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. This approach, though, is less protected from error and decreases the noise immunity.
SR3H SR3M SR3L
ISELH ISELL
TABLE 6. CONTROL REGISTER (SR4) R, W R, W R, W R, W EN R, W R, W R, W VTOP R, W VBOT
SR4H SR4M SR4L
Transmitted Data (I2C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR2 thru SR4) of the ISL6423B via I2C bus. These will be written by the microprocessor as shown below. The spare bits of registers can be used for other functions.
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FN6412.1 April 10, 2007
TABLE 7. STATUS REGISTER SR1 CONFIGURATION SR1H 0 0 0 0 0 0 0 0 0 0 0 SR1M 0 0 0 0 0 0 0 0 0 0 0 SR1L 0 0 0 0 0 0 0 0 0 0 0 OTF X X X X X X X X X 0 1 CABF X X X X X X X 0 1 X X OUVF X X X X X 0 1 X X X X OLF X 0 1 X X X X X X X X BCF X X X 0 1 X X X X X X SR1 is selected IOUT set limit, Normal Operation IOUT > Static/Dynamic Limiting Mode/Power blocks disabled Iobck set limit, Normal Operation Iobck > Dynamic Limiting Mode / Power blocks disabled VIN/VOUT within specified range VIN/VOUT is not within specified range Cable is connected, Io is >20mA Cable is open, Io <2mA TJ 130C, Normal operation TJ >150C, Power blocks disabled FUNCTION
TABLE 8. TONE REGISTER SR2 CONFIGURATION SR2H 0 0 0 0 0 0 SR2M 0 0 0 0 0 0 SR2L 1 1 1 1 1 1 ENT X 0 0 1 X X MSEL X 0 1 0 X X TTH X X X X 0 1 X X X X X X X X X X X X X X SR2 is selected Int Tone = 22kHz, modulated by EXTM, Tr, Tf = 10s typ Ext 22k modulated input, Tr, Tf = 10s typ Int Tone = 22kHz, modulated by ENT bit, Tr, Tf = 10s typ TXT = 0; Decoder Rx threshold is set at 200mV max TXT = 0; Decoder Tx threshold is set at 400mV min FUNCTION
NOTE: X indicates "Read Only" and is a "Don't Care" for the Write mode.
TABLE 9. COMMAND REGISTER SR3 CONFIGURATION SR3H 0 0 0 0 0 0 0 0 0 SR3M 1 1 1 1 1 1 1 1 1 SR3L 0 0 0 0 0 0 0 0 0 DCL X 0 0 0 0 1 0 X X VSPEN X X X X X X X 0 1 X X X X X X X X X X ISELH X 0 0 1 1 X X X X X X ISELL X 0 1 0 1 X SR3 is selected IOUT limit threshold = 305mA typ. IOUT limit threshold = 570mA typ. IOUT limit threshold = 705mA typ. IOUT limit threshold = 890mA typ. Dynamic current limit NOT selected Dynamic current limit selected SELVTOP H/W pin Enabled SELVTOP H/W pin Disabled FUNCTION
NOTE: X indicates "Read Only" and is a "Don't Care" for the Write mode.
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FN6412.1 April 10, 2007
TABLE 10. CONTROL REGISTER SR4 CONFIGURATION SR4H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR4M 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SR4L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EN 1 1 1 1 1 1 1 1 1 1 1 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X VTOP 0 0 0 1 1 0 0 1 1 0 0 1 1 X VBOT 0 0 1 0 1 0 1 0 1 0 1 0 1 X SR4 is selected VSPEN = SELVTOP = 0, VOUT = 13V, VBOOST = 13V + VDROP VSPEN = SELVTOP = 0, VOUT = 14V, VBOOST = 14V + VDROP VSPEN = SELVTOP = 0, VOUT = 13V, VBOOST = 13V + VDROP VSPEN = SELVTOP = 0, VOUT = 14V, VBOOST = 14V + VDROP VSPEN = 0,SELVTOP = 1, VOUT = 18V, VBOOST = 18V + VDROP VSPEN = 0,SELVTOP = 1, VOUT = 18V, VBOOST = 18V + VDROP VSPEN = 0,SELVTOP = 1, VOUT = 19V, VBOOST = 19V + VDROP VSPEN = 0,SELVTOP = 1, VOUT = 19V, VBOOST = 19V + VDROP VSPEN = 1,SELVTOP = X VOUT = 13V, VBOOST = 13V + VDROP VSPEN = 1,SELVTOP = X VOUT = 14V, VBOOST = 14V + VDROP VSPEN = 1,SELVTOP = X VOUT = 18V, VBOOST = 18V + VDROP VSPEN = 1,SELVTOP = X VOUT = 19V, VBOOST = 19V + VDROP PWM and Linear for channel 1 disabled FUNCTION
NOTE: X indicates "Read Only" and is a "Don't Care" for the Write mode.
Received Data (I2C bus READ MODE)
The ISL6423B can provide to the master a copy of the system register information via the I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following Master generated clock bits, the ISL6423B issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: * Acknowledge the reception, starting in this way the transmission of another byte from the ISL6423B. * Not acknowledge, stopping the read mode communication. The read only bits of the register SR1 convey diagnostic information about the ISL6423B, as indicated in the Table 7.
ADDR0 and ADDR1 Pins
Connecting these pin to GND the chip I2C interface address is 0001000, but, it is possible to choose between four different addresses by setting these pins to the logic levels indicated in Table 11.
TABLE 11. ADDRESS PIN CHARACTERISTICS VADDR VADDR-1 "0001000" VADDR-2 "0001001" VADDR-3 "0001010" VADDR-4 "0001011" ADDR1 0 0 1 1 ADDR0 0 1 0 1
Power-On I2C Interface Reset
The I2C interface built into the ISL6423B is automatically reset at power-on. The I2C interface block will receive a Power OK logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the interface will not respond to any I2C commands and the system register SR1 thru SR4 are all initialized to all zero, thus keeping the power blocks disabled. Once the VCC rises above UVLO, the POWER OK signal to the I2C is asserted high, and the I2C interface becomes operative and the SR's can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the Power-On reset circuit. (I2C comes up with EN = 0; EN goes HIGH at the same time as (or later than) all other I2C data for that PWM becomes valid).
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FN6412.1 April 10, 2007
I2C Bit Description
BIT NAME EN VTOP VBOT ENT MSEL DCL VSPEN DESCRIPTION ENable Output for channels 1 and 2 Voltage TOP select i.e. 18V, 19V for channels 1 and 2 Voltage BOTtom select i.e. 13V, 14V for channels 1 and 2 ENable Tone Modulation SELect Dynamic Current Limit select Voltage Select Pin ENable
I2C Electrical Characteristics
TABLE 12. PARAMETER Input Logic High, VIH Input Logic Low, VIL Input Logic Current, IIL Input Logic Current IOL Input Hysteresis SCL Clock Frequency Input Filter Spike reject TEST CONDITION SDA, SCL SDA, SCL SDA, SCL; 0.4V < VDD< 3.3V VOL = 0.4V SDA, SCL 3mA 165mV 0 200mV 100kHz 50ns 235mV 400kHz MIN 2.0V 0.8V 10A TYP MAX
ISELH Current limit "I" SELect High and Low bit and ISELL OTF CABF OUVF OLF BCF TTH Over Temperature Fault bit CABle Fault or open status bit Over and Under Voltage Fault status bit Over Load Fault status bit Backward Current Fault bit Tone THreshold is the OR of the signal pin TXT
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FN6412.1 April 10, 2007
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06
4X 2.5 4.00 A B 19 20X 0.50 24 PIN #1 CORNER (C 0 . 25)
PIN 1 INDEX AREA
18
1
4.00
2 . 50 0 . 15
13
(4X)
0.15 12 7 0.10 M C A B 0 . 07 24X 0 . 23 + 0 . 05 4 24X 0 . 4 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 0 . 1
( 3 . 8 TYP )
C BASE PLANE
SIDE VIEW
SEATING PLANE 0.08 C
(
2 . 50 ) ( 20X 0 . 5 )
C ( 24X 0 . 25 ) ( 24X 0 . 6 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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FN6412.1 April 10, 2007
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
N INDEX AREA E E1 -B1 2 3 TOP VIEW 0.05(0.002) -AD -CSEATING PLANE A L 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M28.173B
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1
A2 c A1 0.10(0.004) C AM BS
MILLIMETERS MIN 0.05 0.80 0.19 0.09 9.60 4.30 6.25 0.45 28 8 0 8 5.50 3.0 MAX 1.20 0.15 1.05 0.30 0.20 9.80 4.50 6.50 0.75 NOTES 9 3 4 6 7 11 11 Rev. 0 6/05
MIN 0.002 0.031 0.0075 0.0035 0.378 0.169 0.246 0.0177 28 0 -
MAX 0.047 0.006 0.051 0.0118 0.0079 0.386 0.177 0.256 0.0295
e E L N
0.026 BSC
0.65 BSC
e
b 0.10(0.004) M
P P1 NOTES:
0.138 0.118
1
2
3
P1
N P BOTTOM VIEW
1. These package dimensions are within allowable dimensions of JEDEC MO-153-AET, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 11. Dimensions "P" and "P1" are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN6412.1 April 10, 2007

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